First-in, first-out (FIFO) memories are typically used to control data communication from a relatively fast electronic device, such as a microprocessor, to a relatively slower device such as a terminal. Typical FIFO memories have a plurality of cells arranged in rows and columns. A read counter is used to address a location in the memory to be read, and a write counter is used to point to a location into which data is to be written. The read counter is incremented to a next read location responsive to the receipt of a read request that originates from one of the deices to which it is connected. The write counter is incremented responsive to the receipt of a write request that originates from the other of the connected devices.
In a previously developed FIFO design, an up/down counter is used to count the difference between the number of read requests and write requests received by the read and write counters. These read and write requests are generated asynchronously. A problem has occurred in accurately recording the above-described difference when the write and read requests arrive closely or simultaneously in time. Without somehow regulating these requests, there is a danger that only one will be recorded and the other lost.
A need has therefore arisen for an arbiter between external read and write signals that will decide which of the signals is to be given priority while storing the other for use to actuate a subsequent operation.